Forming strained fins of different materials on a substrate

ABSTRACT

A method, and the resulting structure, of forming two fins with different types of strain and material on the same substrate.

BACKGROUND

The present invention relates to semiconductor devices, and particularlyto forming fins of two different semiconductor materials on the samesubstrate.

Fin field effect transistors (FinFETs) are an emerging technology whichmay provide solutions to field effect transistor (FET) scaling problemsat, and below, the 22 nm node. FinFET structures may include at least anarrow semiconductor fin gated on at least two sides of each of thesemiconductor fin, as well as a source region and a drain regionadjacent to the fin on opposite sides of the gate. FinFET structureshaving n-type source and drain regions may be referred to as nFinFETs,and FinFET structures having p-type source and drain regions may bereferred to as pFinFETs.

In some FinFET structures, different materials may be used for the finsof pFinFETs and nFinFETs in order to improve device performance.However, a material or property that may improve pFinFET performance mayreduce nFET performance, and vice versa. For example, while pFinFETperformance may be improved by forming fins made of silicon-germanium,nFinFET performance may instead be improved by forming fins made ofundoped or carbon-doped silicon and may be degraded by forming fins madeof silicon-germanium. Further, pFinFETs and nFinFETs are oftenfabricated on the same substrate.

BRIEF SUMMARY

An embodiment of the invention may include a method of forming asemiconductor. A first strained fin may be formed in a first region of asemiconductor substrate, and a strained mandrel may be formed in asecond region of a semiconductor substrate. The semiconductor substratemay be a strained semiconductor material and the first strained fin ismade of a first strained material. The first region of the semiconductorsubstrate may be masked, and the strained mandrel in the second regionmay be relaxed to form an unstrained mandrel. A second material may beepitaxially grown on the unstrained mandrel to form a second strainedfin, wherein the material of the first strained fin is different fromthe material of the second strained fin. The mask in the first region ofthe semiconductor substrate may be removed.

Another embodiment of the invention may include a method of forming asemiconductor. A first strained fin may be formed in a nFET region of asemiconductor substrate, and a strained mandrel may be formed in a pFETregion of a semiconductor substrate. The semiconductor substrate may bea strained semiconductor material and the first strained fin is made ofa first strained material. The nFET region of the semiconductorsubstrate may be masked, and the strained mandrel in the second regionmay be relaxed to form an unstrained mandrel. A second material may beepitaxially grown on the unstrained mandrel to form a second strainedfin, wherein the material of the first strained fin is different fromthe material of the second strained fin. The mask in the nFET region ofthe semiconductor substrate may be removed.

Another embodiment of the invention may include a semiconductorstructure. A first fin may be located on a substrate, and the first finmay be made of a first strained semiconductor material. A second fin maybe located on the substrate, and the second fin may be made of a secondstrained semiconductor material.

BRIEF DESCRIPTION OF THE SEVERAL DRAWINGS

FIG. 1 is a cross-sectional view of a structure containing mandrelslocated on a hardmask covering a SOI substrate, according to an exampleembodiment;

FIG. 2 is a cross-sectional view of masking a second region of thestructure, according to an example embodiment;

FIG. 3 is a cross-sectional view of formation of sidewall spacers nextto the exposed mandrels, according to an example embodiment;

FIG. 4 is a cross-sectional view of removing the mandrels from the firstregion and the mask from the second region of the structure, accordingto an example embodiment;

FIG. 5 is a cross-sectional view after etching the fin and mandrelpattern to the underlying semiconductor, according to an exampleembodiment;

FIG. 6 is a cross-sectional view of masking the first region of thestructure, according to an example embodiment;

FIG. 7 is a cross-sectional view after relaxing the mandrels in thesecond region of the semiconductor structure, according to an exampleembodiment;

FIG. 8 is a cross-sectional view of fins epitaxially grown on therelaxed mandrels in the second region, according to an exampleembodiment;

FIG. 9 is a cross-sectional view of removing the hardmask above therelaxed mandrels, according to an example embodiment;

FIG. 10 is a cross-sectional view of removing the relaxed mandrels,according to an example embodiment; and

FIG. 11 is a cross-sectional view of the formed fins, according to anexample embodiment.

Elements of the figures are not necessarily to scale and are notintended to portray specific parameters of the invention. For clarityand ease of illustration, dimensions of elements may be exaggerated. Thedetailed description should be consulted for accurate dimensions. Thedrawings are intended to depict only typical embodiments of theinvention, and therefore should not be considered as limiting the scopeof the invention. In the drawings, like numbering represents likeelements.

DETAILED DESCRIPTION

Example embodiments now will be described more fully herein withreference to the accompanying drawings, in which example embodiments areshown. This disclosure may, however, be embodied in many different formsand should not be construed as limited to the example embodiments setforth herein. Rather, these example embodiments are provided so thatthis disclosure will be thorough and complete and will fully convey thescope of this disclosure to those skilled in the art. In thedescription, details of well-known features and techniques may beomitted to avoid unnecessarily obscuring the presented embodiments.

For purposes of the description hereinafter, terms such as “upper”,“lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, andderivatives thereof shall relate to the disclosed structures andmethods, as oriented in the drawing figures. Terms such as “above”,“overlying”, “atop”, “on top”, “positioned on” or “positioned atop” meanthat a first element, such as a first structure, is present on a secondelement, such as a second structure, wherein intervening elements, suchas an interface structure may be present between the first element andthe second element. The term “direct contact” means that a firstelement, such as a first structure, and a second element, such as asecond structure, are connected without any intermediary conducting,insulating or semiconductor layers at the interface of the two elements.

In the interest of not obscuring the presentation of embodiments of thepresent invention, in the following detailed description, someprocessing steps or operations that are known in the art may have beencombined together for presentation and for illustration purposes and insome instances may have not been described in detail. In otherinstances, some processing steps or operations that are known in the artmay not be described at all. It should be understood that the followingdescription is rather focused on the distinctive features or elements ofvarious embodiments of the present invention.

Introducing stresses or strains into semiconductor materials mayincrease the performance of a semiconductor device made from thatmaterial. Additionally, structures like Field Effect Transistors (FETs)may benefit from using different materials in order to create structureswith different functions, such as pFETs and nFETS. Additionally, FinFETstructures may allow for smaller semiconductor structures, which mayincrease device performance. Thus, creating at least 2 types ofsemiconductor fins on the same device may allow for optimization of twodifferent structures. For example, using strained silicon for creatingfins for nFETs, and strained silicon-germanium for fins in a pFET, mayallow one to create better performing semiconductor devices. This may beaccomplished by transferring a fin pattern into a first region and amandrel pattern into a second region of a strained semiconductormaterial, like strained silicon. The first region may then be masked,and the second region may be altered to release the strain in themandrels. A second semiconductor material may be epitaxially grown onthe unstrained mandrels. This may introduce strain into the secondsemiconductor material if the unstrained mandrel has a significantlydifferent crystalline structure. Once the mandrel is removed, astructure may be present where a first fin and a second fin arestrained, and the first and second fin are made of different materials.

Referring now to FIG. 1, mandrels 150 may be formed above a hardmasklayer 140, located on a substrate 100. The substrate 100 may include abulk semiconductor or a layered semiconductor such as Si/SiGe, asilicon-on-insulator, or a SiGe-on-insulator, or any other semiconductoron insulator (SOI) structure. Bulk substrate materials may includeundoped Si, n-doped Si, p-doped Si, single crystal Si, polycrystallineSi, amorphous Si, Ge, SiGe, SiC, SiGeC, Ga, GaAs, InAs, InP and allother III/V or II/VI compound semiconductors. If the substrate 100 is anSOI may further include a buried insulator layer 120 below the SOI layer130, and a base semiconductor layer 110 below the buried insulator layer120. The buried insulator layer 120 may isolate the SOI layer 130 fromthe base semiconductor layer 110. The base semiconductor layer 110 maybe made from any of several known semiconductor materials such as, forexample, silicon, germanium, silicon-germanium alloy, carbon-dopedsilicon, carbon-doped silicon-germanium alloy, and compound (e.g. III-Vand II-VI) semiconductor materials. Non-limiting examples of compoundsemiconductor materials include gallium arsenide, indium arsenide, andindium phosphide. Typically the base semiconductor layer 110 may beapproximately, but is not limited to, several hundred microns thick. Forexample, the base semiconductor layer 110 may have a thickness rangingfrom approximately 0.5 mm to approximately 1.5 mm. The SOI substrate 100may contain a second region 102 and a first region 101 which may beeffectively undergo different processing steps in order to form finshaving different properties.

The buried insulator layer 120 may be formed from any of severaldielectric materials. Non-limiting examples include, for example,oxides, nitrides, oxynitrides of silicon, and combinations thereof.Oxides, nitrides and oxynitrides of other elements are also envisioned.In addition, the buried insulator layer 120 may include crystalline ornon-crystalline dielectric material. The buried insulator layer 120 maybe 40-500 nm thick.

The SOI layer 130 may be made of any of the several semiconductormaterials possible for the base semiconductor layer 110. In general, thebase semiconductor layer 110 and the SOI layer 130 may include eitheridentical or different semiconducting materials with respect to chemicalcomposition, dopant concentration and crystallographic orientation. Inan example embodiment, the SOI layer 130 comprises silicon,silicon-germanium, or carbon-doped silicon. The SOI layer 130 may bedoped with p-type dopants, such as boron, or doped with n-type dopants,such as phosphorus and/or arsenic. The dopant concentration may rangefrom approximately 1×10¹⁵ cm⁻³ to approximately 1×10¹⁹ cm⁻³, preferablyapproximately 1×10¹⁵ cm⁻³ to approximately 1×10¹⁶ cm⁻³. In the exampleembodiment, the SOI layer 130 is undoped. The SOI layer 130 may have athickness ranging from approximately 5 nm to approximately 300 nm,preferably approximately 30 nm.

A SOI substrate 100 is illustrated in the figures and is relied upon forthe corresponding discussion. In the example embodiment, the SOI layermay be a strained silicon or strained silicon-germanium material. Thehardmask layer 140 may include multiple layers. In one embodiment, thehardmask layer 140 may include silicon oxide, silicon nitride, ametal-nitride, such as titanium-nitride (TiN), boron-nitride (BN), or ametal-oxide, or any combination thereof. Further, in some embodiments,the hardmask layer 140 may have a thickness, ranging from about 5 nm toabout 80 nm.

The mandrel 150 may be generated using known photolithography andmasking techniques. During this step, a mandrel layer may be formed ontop of the hardmask layer 140. The mandrel layer may include amorphoussilicon or any silicon based compound, for example, silicon nitride,silicon oxide, or silicon carbon, or alternatively amorphous carbon. Themandrel layer may preferably include a material that is different enoughfrom the material of the sidewall spacers 170 (described below) and thematerial of the hardmask layer 140 so that it may be selectivelyremoved. The particular material chosen may partly depend upon thedesired pattern to be formed and the materials chosen in subsequentsteps discussed below. In one embodiment, the mandrel layer may beformed with a vertical thickness ranging from about 30 nm to about 150nm. The mandrel layer may then be lithographically patterned to createthe mandrel 150. The mandrel 150 may be formed by applying knownpatterning techniques involving exposing a photo-resist and transferringthe exposed pattern of the photo-resist by etching the mandrel layer.

Referring now to FIG. 2, in the example embodiment the mandrels 150 ofthe second region 102 may be protected with a first masking structure160. The first masking structure 160 may be used to eliminate depositionon the mandrel 150 in the second region 102, while allowing depositionon the mandrel 150 in the first region 101. This may allow thesubsequent formation of a fin pattern in the first region 101, andmaintain the mandrel 150 pattern in the second region 102. Morespecifically, the method may include masking the second region 102 ofthe semiconductor by forming a masking layer, patterning at least thesecond region 102, and etching the masking layer from the unprotectedregions. The masking layer may include an oxide (e.g. silicon oxide), anitride (e.g. silicon nitride) or any combinations thereof. Patterningof the desired region may be done through lithographic techniques.Etching the masking layer may be accomplished through any combination ofknown techniques, such as, for example, RIE, wet stripping and plasmaetching.

Referring now to FIG. 3, in the example embodiment sidewall spacers 170may be formed adjacent to the mandrel 150 by conformally depositing alayer of dielectric material (hereinafter “dielectric layer”) directlyon top of the hardmask layer 140 and the mandrel 150. In one embodiment,the dielectric layer may include, for example, silicon nitride orsilicon oxide. It should be noted, however, that the dielectric layershould be of a material capable of being removed selective to thehardmask layer 140. For example, if the hardmask layer 140 is an oxidethen the dielectric layer may preferably be a nitride, or alternatively,if the hardmask layer 140 is a nitride then the dielectric layer maypreferably be an oxide. The dielectric layer may be deposited with aconformal deposition technique, using any known atomic layer depositiontechnique, molecular layer deposition techniques, or future developeddeposition technique. In an embodiment, the dielectric layer may have asubstantially uniform thickness. In that embodiment, the dielectriclayer may have a conformal and uniform thickness ranging from about 5 nmto about 50 nm.

Following deposition of the dielectric material, sidewall spacers 170may be formed by subjecting the dielectric layer to a directionaletching process such as a reactive-ion-etching technique. Thedirectional etching process may remove a portion of the dielectric layerfrom above the hardmask layer 140 and from the top of the mandrel 150. Aportion of the dielectric layer may remain along opposite sidewalls ofthe mandrel 150, forming the sidewall spacers 170. Furthermore, themandrel 150 and the sidewall spacers 170 should each include materialsthat would allow the mandrel 150 to be subsequently removed selective tothe sidewall spacers 170. Here, it should also be noted that thesidewall spacers 170 depicted in FIGS. 3 and 3A are for illustrationpurposes and generally may have a slightly different shape from thoseshown. For example, the sidewall spacers 170 may have rounded cornersthat may be naturally formed during the directional etching process asis known in the art. The sidewall spacers 170 will eventually define afin pattern which ultimately may be transferred into the underlyingsubstrate 100.

Referring now to FIG. 4, in the example embodiment the mandrels 150 inthe first region 101 and the first masking structure 160 in the secondregion 102 may be removed. This may create the final structures to betransferred to the underlying semiconductor material. First, the mandrel150 may be removed selective to the sidewall spacers 170. Anon-selective breakthrough etch may be applied to exposed the mandrel150. In one embodiment, the mandrel 150 is silicon, and the sidewallspacers 170 is an oxide. In such cases, the silicon may be removedselective to the oxide. Furthermore, the mandrel 150 may be removedselective to the hardmask layer 140. In one embodiment, the mandrel 150may be removed using a typical standard clean technique, includingammonium hydroxide and hydrogen peroxide, in which the sidewall spacers170 will not be trimmed. Removing the first masking structure 160 may beaccomplished by any suitable means, such as RIE, plasma etching andwetstripping the first masking structure 160.

Referring now to FIG. 5, in the example embodiment the pattern istransferred to the underlying semiconductor material. More specifically,a fin pattern defined by the sidewall spacers 170 may be transferredinto the substrate 100 using a multi-sequence etching technique. First,the hardmask layer 140 may be etched to expose the substrate 100. Adirectional etching technique such as a reactive-ion-etching techniquemay be used to etch the exposed hardmask layer 140, to create a finhardmask 240 and a mandrel hardmask 245. In one embodiment, where thehardmask layer 140 is an oxide, a reactive-ion-etching technique using afluorocarbon based etchant with additional gases such as O₂ or Ar may beused. In the present step, the sidewall spacers 170 and mandrel 150 mayfunction as a mask, and may have high etch selectivity relative to thehardmask layer 140.

Next, the semiconductor layer 130 of the substrate 100 may then beetched to a desired depth. The desired depth may depend on the ultimatefunction of the structure 10. A directional etching technique such as areactive-ion-etching technique, such as described above, may be used toetch the substrate 100. In one embodiment, the substrate 100 may beetched with a reactive-ion-etching technique using a chlorine or abromine based etchant. In the present step, the hardmask layer 140 mayfunction as a mask, and may have a high etch-selectivity relative to thesubstrate 100. In an embodiment, the semiconductor layer 130 may beetched all the way down to the oxide layer 120. Following the etch, atleast a first fin 250 and a set of semiconductor mandrels 255, areformed. Following the etch, the fin hardmask 240 is located above eachfirst fin 250, and the mandrel hardmask 245 is located above eachsemiconductor mandrel 255.

Referring now to FIG. 6, in the example embodiment the first region 101is covered with a second masking structure 270. The second maskingstructure 270 ensures that the strained fins will maintain the strainduring subsequent processing. More specifically, the method may includemasking a region of the semiconductor by forming a masking layer,patterning the desired region, and etching the masking layer from theunprotected regions. The masking layer may include an oxide (e.g.silicon oxide), a nitride (e.g. silicon nitride) or any combinationsthereof. Patterning of the desired region may be done throughlithographic techniques, to the desired structure. Etching the secondmasking structure 270 may be accomplished through any combination ofknown techniques, such as, for example, RIE, wet stripping and plasmaetching.

Referring now to FIG. 7, in the example embodiment the mandrels 255(FIG. 6) in the second region 102 may be relaxed to form relaxedmandrels 257. Relaxing the mandrels 255 in the second region 102 maychange the crystal lattice of the material. This may allow for adifferent semiconductor material to be epitaxially grown on thesidewalls of the relaxed mandrels, to impart the crystal lattice of arelaxed material from the SOI layer 130 (FIG. 4). In instances where thecrystal lattices of the relaxed semiconductor material of the SOI layer130, and the epitaxially grown semiconductor material, are sufficientlydifferent, this may impart stresses or strains into the epitaxiallygrown semiconductor. Relaxing the strained semiconductor material may beaccomplished through any known means, such as a thermal anneal, ionimplantation combined with recrystallization method or any other meansof chemical addition. In an example embodiment, where the semiconductormaterial is strained silicon, the strain may be released using a thermalanneal in the presence of hydrogen.

Referring now to FIG. 8, in the example embodiment at least a second fin260 of a semiconductor material of a material different from that in theSOI layer 130 may be epitaxially grown on the sidewalls of the relaxedmandrel 257 in the second region 102. The semiconductor material may beany semiconductor material, such as the semiconductor materials listedabove. In an example embodiment, the semiconductor material may besilicon-germanium. In such embodiments, the silicon germanium materialmay contain, for example, approximately 20% to approximately 100%germanium, approximately 0% to approximately 80% silicon, and may bedoped with p-type dopants such as boron in concentrations ranging fromapproximately 1×10¹⁵ atoms/cm³ to approximately 5×10¹⁸ atoms/cm³. Inother example embodiments, the semiconductor material 170 may be carbondoped silicon. In such embodiment, the silicon germanium material maycontain, for example, approximately 0.5% to approximately 2.5% carbon,approximately 97.5% to approximately 99.5% silicon, and may be dopedwith n-type dopants such as arsenic or phosphorus in concentrationsranging from approximately 1×10¹⁵ atoms/cm³ to approximately 5×10¹⁸atoms/cm³. In an example embodiment, semiconductor mandrel 255 may besilicon, and the semiconductor material may be silicon-germanium. Insuch an embodiment, epitaxially growing silicon-germanium on silicon mayimpart stress into the silicon-germanium crystal lattice.

The terms “epitaxial growth and/or deposition” and “epitaxially formedand/or grown” mean the growth of a semiconductor material on adeposition surface of a semiconductor material, in which thesemiconductor material being grown may have the same crystallinecharacteristics as the semiconductor material of the deposition surface.In an epitaxial deposition process, the chemical reactants provided bythe source gases are controlled and the system parameters are set sothat the depositing atoms arrive at the deposition surface of thesemiconductor substrate with sufficient energy to move around on thesurface and orient themselves to the crystal arrangement of the atoms ofthe deposition surface. Therefore, an epitaxial semiconductor materialmay have the same crystalline characteristics as the deposition surfaceon which it may be formed. For example, an epitaxial semiconductormaterial deposited on a {100} crystal surface may take on a {100}orientation. In some embodiments, epitaxial growth and/or depositionprocesses may be selective to forming on semiconductor surfaces, and maynot deposit material on dielectric surfaces, such as silicon dioxide orsilicon nitride surfaces. In embodiments where the semiconductormaterial has a different lattice constant from the deposition surface,the semiconductor material may take on the lattice structure of thedeposition surface, which may impart stresses or strains into theepitaxially grown semiconductor material.

Referring now to FIG. 9, in the example embodiment the mandrel hardmask245 is removed from above the semiconductor mandrel 150 in the secondregion 102. Removing the mandrel hardmask 245 may be accomplished by anysuitable means, such as RIE, plasma etching and wetstripping.

Referring now to FIG. 10, in the example embodiment the semiconductormandrel 255 is removed from the second region 102. More specifically,the semiconductor mandrel 255 may be removed selective to the secondfins 260. This may be performed using any means capable of selectivelyremoving the semiconductor material such as, for example, TMAH solutioncan be used to etch Si selective to SiGe.

Referring now to FIG. 11, in the example embodiment the second maskingstructure 270 and the fin hardmask 240 may be removed from the firstregion 101. Removing the second masking structure 270 and the finhardmask may be accomplished by any suitable means, such as RIE, plasmaetching and wetstripping.

Following the removal of the second masking structure 270 and the finhardmask 245, a first semiconductor fin 250 and a second semiconductorfin 260 may be located on the same device. The material for the firstfin 250 and the second semiconductor fin 260 may be selected that thereis a lattice mismatch between the materials, such that when the materialof the second semiconductor fin 260 is epitaxially grown on the materialof the first fin 250, a strain is introduced into the crystal lattice ofthe first material. In an example embodiment, the first material may besilicon and the second material may be silicon-germanium. In the exampleembodiment, a fin pattern in a first region 101 and a mandrel pattern ina second region 102 may be introduced into a strainedsilicon-on-insulator substrate. The mandrels in the second region may berelaxed prior to epitaxial growth of silicon-germanium to create thesecond semiconductor fins 260, which may be strained due to the latticemismatch between silicon and silicon-germanium. This may create asilicon fin with tensile strain on the same device as a silicongermanium fin with compressive strain. This may allow for increasedperformance of devices made from these fins, such as nFETs and pFETs.

The descriptions of the various embodiments of the present inventionhave been presented for purposes of illustration, but are not intendedto be exhaustive or limited to the embodiments disclosed. Manymodifications and variations will be apparent to those of ordinary skillin the art without departing from the scope and spirit of the describedembodiments. The terminology used herein was chosen to best explain theprinciples of the embodiment, the practical application or technicalimprovement over technologies found in the marketplace, or to enableother of ordinary skill in the art to understand the embodimentsdisclosed herein. It is therefore intended that the present inventionnot be limited to the exact forms and details described and illustratedbut fall within the scope of the appended claims.

What is claimed is:
 1. A semiconductor structure comprising: a first finlocated on a substrate, wherein the first fin comprises a first strainedsemiconductor material; and a second fin located on the substrate,wherein the second fin comprises a second strained semiconductormaterial.
 2. The structure of claim 1, wherein the first strainedsemiconductor material is strained silicon.
 3. The structure of claim 1,wherein the second strained semiconductor material is strained silicongermanium.
 4. The structure of claim 1, wherein the first strainedsemiconductor material has a tensile strain.
 5. The structure of claim1, wherein the second strained semiconductor material has a compressivestrain.
 6. The structure of claim 1, wherein the substrate is asemiconductor-on-insulator substrate.